The present application relates generally to the field of electrical signal integrity and more specifically to circuits for improving electrical signal integrity. Description of the Related Art
As the demand on the performance of electronic systems increase, the systems include higher speed processors and higher memory densities with relatively heavy fan-outs. However, higher speed processors and higher memory densities translate to higher power dissipation and increased memory access time, impairing the performance of the system.
Traditional systems sometimes incorporate multiplexers and/or demultiplexers to help quiet inactive signal paths, minimizing the overall dynamic power dissipation, and isolating unused subsystems. FIG. 1 schematically illustrates an example of such a system 10 which incorporates a multiplexer-demultiplexer 12 to isolate unused subsystems of a plurality of subsystems 16, 18. This arrangement can reduce the load on each driver 14 when the original signal path includes multiple destinations by inserting a multiplexer on each signal path between the driver 14, the receiver 20 and the multiple destinations. However, the multiplexer and/or demultiplexer 12 can present transmission line discontinuity regions in electronic systems (e.g., in electronic systems with signal paths with electrical lengths longer than ¼ of the wavelength of the operational frequency or the signal transition rate). In such systems, signal reflections may occur, changing wave characteristics and degrading system performance. These signal reflections may cause signal distortions and signal integrity issues which can contribute to reduced system performance and eventual failure of the system, thereby limiting the effectiveness of the multiplexer and/or demultiplexer in addressing the signal integrity and power dissipation issues.
In memory applications, some systems control “chip select” or device select signals, along with the memory address and control signals, based on the device select signals, in order to disable memory devices when they are not being accessed. FIG. 2 schematically illustrates an example of such a system 20 which isolates unused subsystems of a plurality of subsystems 16, 18 using device select signals 22, 24 (e.g., chip select signals). The devices are disabled by not activating (asserting) the address, control, and/or device select signals, thus logically isolating the memory devices which are not accessed. This arrangement generally requires a device select signal for each physical memory rank and the address and device. select signals are generally controllable based on whether the corresponding memory device or group of memory devices is being accessed. Generating controllable address and device select signals can introduce timing delays on the device select, address, and control paths. In addition, this arrangement does not address the power dissipation and may degrade performance degradation by, for example, requiring that secondary control signals be generated for the memory devices.